1. Field of the Invention
The present invention relates to a data input buffer circuit, and in particular to a data input buffer circuit which is capable of decreasing a current consumption caused when a data signal is transited in a write disable interval by maintaining a state that a data signal is transited in a write enable interval in the write enable interval and accurately reading and writing data by obtaining a substantial data holding time(tDH) margin.
2. Description of the Background Art
FIG. 1 illustrates a conventional input buffer circuit which includes a first basic input data buffer circuit 11 which includes a first NOR-gate NOR1 for NORing a data control signal WECS formed by mixing a write enable signal WE and a chip selection signal CS and a first data signal DIN1 inputted into an external first data pad, a first inverter INV1 for inverting an output of the first NOR-gate NOR1, a first delay unit DE1 for delaying an output of the first inverter INV1 for a certain time Td1 and outputting a first input data signal DATAIN1, and a first data transition detection unit 20 for detecting a transition of the first data control signal DINT1 from the first inverter INV1 and outputting a first data transition detection signal DTD1. There are further provided data transition detection units 21.about.1n for receiving second.about.n-h data signals DIN2.about.DINn, and a data transition detection signal mixing unit 30 for mixing first.about.n-th data transition detection signals DTD1.about.DTDn outputted from the data transition detection units 2.about.2n of the first.about.n-h basic data input buffer circuits 11.about.1n which are configured in a similar method compared to the first basic input data buffer circuit 11.
The number of basic data input buffer circuits is determined depending on the number of input/output pins.
FIG. 2 illustrates a first data transition detection unit 21. As shown therein, there are provided a second inverter INV2 for inverting a first data control signal DINT1 from the first inverter INV1, a second delay unit DE2 for delaying an output of the second inverter INV2 for a certain time, a third inverter INV3 for inverting an output of the second delay unit DE2, first and second transmission gates TG1 and TG2 controlled by an output of the second delay unit DE2 and an inverted signal thereof for selectively transmitting a first data control signal DINT2 from the first inverter INV1 and an inverted signal thereof, a fourth inverter INV4 for inverting an output from the first or second transmission gates TG1 or TG2, and a first NMOS transistor NM1 for receiving an output of the fourth inverter INV4 via its gate and outputting a first data transition detection signal DTD1 via its drain. In addition, the construction of a data transition detection unit(not shown) of the second through n-th basic data input buffer circuits 12.about.1n is constructed in the same manner as the first data transition detection unit 21.
FIG. 3 is a circuit diagram illustrating a detection signal summing unit 30 for summing the first through n-th data transition detection signals DTD1.about.DTDn. As shown therein, there are provided a first PMOS transistor PM1 and a second NMOS transistor NM2 connected in series between a power voltage VCC and a ground voltage VSS and having their commonly connected drains which receive first through n-th detection signals DTD1.about.DTDn, second through fourth PMOS transistors PM2.about.PM4 connected parallely with the first PMOS transistor PM1, a fifth inverter INV5 for inverting a chip selection signal CS and applying the inverted signal to the second NMOS transistor NM2 and the third PMOS transistor PM3, respectively, a sixth inverter INV6 for inverting the voltages of the commonly connected drains of the fourth PMOS transistor PM3 and the second NMOS transistor NM2 and applying to the gate of the fourth PMOS transistor PM4, a seventh inverter INV7 for inverting an output of the sixth inverter INV6, a third delay unit DE3 for delaying an output of the seventh inverter INV7 for a certain time, a second NOR-gate NOR2 for NORing an output of the third delay unit DE3 and an output of the seventh inverter INV7, a first NAND-gate ND1 for NANDing an output of the second NOR-gate NOR2 and a chip selection signal CS and outputting to the gates of the first and second PMOS transistors PM1 and PM2, respectively, and an eighth inverter INV8 for inverting a voltages of the commonly connected drains of the first through fourth PMOS transistors PM1.about.PM4 and the second NMOS transistor NM2 and outputting a summing signal DTDSUM of a data transition detection signal.
The operation of the conventional data input buffer circuit will be explained with reference to the accompanying drawings.
First, as shown in FIGS. 4A and 4B, the write enable signal WE and the chip selection signal CS are summed for thereby generating a write control signal WECS as shown in FIG. 4C. This write control signal WECS is summed with the first data signal DIN1 as shown in FIG. 4D inputted into an external first data pad, so that a first data control signal DINT1 as shown in FIG. 4E is generated.
The first data control signal DINT1 is delayed by the first delay unit DE1 for a certain time and is outputted as a first input data signal DATAIN1 as shown in FIG. 4H.
The first data transition detection unit 21 generates a first data transition detection signal DTD1, as shown in FIG. 4F, for detecting the transition of the first data control signal DINT1.
When the second through n-th data transition detection signals DTD2.about.DTDn are outputted from the second n-th data transition detection units 22.about.2n, the data transition detection signal summing unit 30 sums the first through n-th data transition detection signals DTD1.about.DTDn for thereby generating a data transition detection signal summing signal DTDSUM.
The thusly generated data transition detection signal summing signal DTDSUM is used as a control signal when the semiconductor memory apparatus operates in the write mode.
However, the data control signal is disabled when the write control signal WECS is enabled and even disabled(transited from low to high), so that a current flow path is formed at an unnecessary interval for thereby increasing the current consumption. A data control signal is delated for obtaining a data hold time dDH margin using the first delay unit DE1. In this case, a certain variation may be produced due to various processes. Therefore, in order to obtain an enough data hold time tDH margin, a lot amount of inverters is used for a process margin of the first delay unit DE1 because an input data signal is transited at the write disable interval, and an invalid data may be written.